The inventive concept relates to semiconductor integrated circuits (ICs), and more particularly, to a duty cycle corrector incorporated within an IC capable of correcting a signal duty cycle.
A delay locked loop (DLL) circuit is commonly included in certain semiconductor memory devices, such as the synchronous dynamic random access memory (SDRAM), which operate synchronously with a reference clock signal. The DLL circuit is capable of a very high degree of integration and may therefore be included within contemporary synchronous memory devices. In general operation, the DLL circuit receives an external clock signal and generates an internal clock signal by delaying the external clock signal for a predetermined delay period. The internal clock signal may then be used as a clock signal by various circuits within the memory device.
The DLL circuit may be variously designed and certain designs include a duty cycle corrector configured to correct the duty cycle of a signal. Duty cycle correctors maintain the duty cycle of an output signal at a fixed ratio of (e.g.,) 5:5.
Without a duty cycle corrector, the DLL circuit may generate the internal clock signal at a duty cycle other than the prescribed ratio. If this happens, an associated transfer window (i.e., a defined period of time during which data/address/control signals are transferred) may become impaired and create the risk of errant signal transfers. For example, input/output data may not be accurately latched or transferred to/from the memory device. Thus, duty cycle correction is performed in order to adjust the duty cycle of a clock signal, such that it remains at a defined ratio (e.g., 5:5). Thus, the operating range of and output characteristics of the duty cycle corrector are influenced by a difference between the duty cycle of a clock signal that is initially applied to the duty cycle corrector (e.g. an output signal received from the DLL circuit) and a target value.
Of additional note, excessive duty cycle correction may deteriorate the output signal characteristics of the duty cycle corrector. Excessive duty cycle correction is likely to occur when duty cycle correction is performed within a low frequency domain.
In general, the duty cycle corrector includes a duty cycle correction amplifier configured to amplify an input clock signal. The duty cycle corrector adjusts the duty cycle of the input clock signal by changing the common mode of the duty cycle correction amplifier using a duty control signal. Accordingly, the range of the common mode is determined by the duty cycle of an initially applied input clock signal.
Figure (FIG.) 1 is a timing diagram illustrating a method of correcting the duty cycle of a high frequency input clock signal and corresponding variation in the common mode. FIG. 2 is a timing diagram illustrating a conventional method of correcting the duty cycle of a low frequency input clock signal and a corresponding variation in the common mode.
As illustrated in FIGS. 1 and 2, duty cycle correction is performed by varying the common mode of an input clock signal ICLK and the common mode of a complementary input clock signal ICLKB in opposite directions. In this case, when a variation Δ in the common mode increases excessively, the output clock signal OCLK may become distorted.
In particular, when the input clock signal ICLK is a relatively low frequency signal, the extent to which the duty cycle of the input clock signal ICLK needs to be adjusted is greater than when the input clock signal ICLK is a high frequency signal. Thus, as illustrated in FIG. 2, if duty cycle correction is continuously performed on a low frequency the input clock signal ICLK (i.e., a clock signal susceptible to excessive duty cycle correction), then the variation Δ in the common mode increases greatly and causes distortion in the output clock signal OCLK. In extreme instances, the output clock OCLK distortion may result in the loss of output clock signal OCLK pulses.